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[VHDL-FPGA-Verilog] Verilog&Vhdl混语言对SDRAM的控制源代码

Description: Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!
Platform: | Size: 249856 | Author: 飞扬 | Hits:

[Other Embeded program] ip

Description: usart的verilog代码.rar 包括很多的FPGA ip 源码，可以直接应用 uart_vhdl.zip sl811usb包含源程序.rar mc8051_design.zip mcpu_1[1].05.zip minicpu.zip mmc_lark_original.zip -USART the Verilog code. rar, including many of the FPGA ip source, can be applied directly uart_vhdl.zipsl811usb contains the source code. rarmc8051_design.zipmcpu_1 [1] .05. zipminicpu.zipmmc_lark_original.zip
Platform: | Size: 5391360 | Author: 钟阳 | Hits:

[VHDL-FPGA-Verilog] 62256

Description: EPM1270和ram62256的verilog接口程序，用QuartusII编译
Platform: | Size: 323584 | Author: 汉武帝 | Hits:

[VHDL-FPGA-Verilog] T4_sdram_control

Description: verilog语言 利用FPGA控制SDRAM，相信很多朋友都需要 快下载吧-control FPGA Verilog language use SDRAM, believe that many of my friends need to download it faster
Platform: | Size: 19456 | Author: 杜菲 | Hits:

[VHDL-FPGA-Verilog] an_dcfifo_top_restored

Description: alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输 ，值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.
Platform: | Size: 928768 | Author: alison | Hits:

[VHDL-FPGA-Verilog] RAM

Description: 双口RAM与PXI总线接口设计，包括接口控制。-Dual-port RAM with PXI bus interface design, including interface control.
Platform: | Size: 1216512 | Author: zwt | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 采用VHDL语言设计一个4通道的数据采集控制模块。系统的功能描述如下： 1.系统主时钟为100 MHz。 2.数据为16位-数据线上连续2次00FF后数据传输开始。 3.系统内部总线宽度为8位。 4.共有4个通道（ch1、ch2、ch3、ch4），每个通道配备100 Bytes的RAM，当存满数据后停止数据采集并且相应通道的状态位产生报警信号。 5.数据分为8位串行输出，输出时钟由外部数据读取电路给出。 6.具备显示模块驱动功能。由SEL信号设置显示的通道，DISPLAY信号启动所选通道RAM中数值的显示过程。数值顺次显示一遍后显示结束，可以重新设定SEL的值选择下一个通道。模块数据线为8位，显示器件为4个8段LED。 7.数据采集模式如下：单通道采集（由SEL信号选择通道），多通道顺次采集（当前通道采满后转入下一通道），多通道并行采集（每通道依次采集一个数据）。模式由控制信号MODE选择，采集数据的总个数由NUM_COLLECT给出。 8.数据采集过程中不能读取，数据读取过程中不能采集-err
Platform: | Size: 5782528 | Author: pengfu | Hits:

[VHDL-FPGA-Verilog] RAM

Description: 用VerilogHDL写的ram程序，对初学者会有帮助。-Writing the ram with VerilogHDL procedures will be helpful for beginners.
Platform: | Size: 271360 | Author: Blakeu | Hits:

[VHDL-FPGA-Verilog] ram_Test

Description: RAM读写控制器，用verilog实现的简单易懂的RAMROMsram控制核-Controller RAM read and write, using verilog implementation of easy-to-understand control of nuclear RAMROMsram
Platform: | Size: 3072 | Author: 王欢 | Hits:

[VHDL-FPGA-Verilog] 256fft

Description:
Platform: | Size: 209920 | Author: Nagendran | Hits:

[VHDL-FPGA-Verilog] NET2

Description: This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, using Veril Verilog language, a hardware-base FPGA embedded project combat, Man Application FPGA, FPGA-chip hardw Mallat implementation of wavelet Layer of one-dimensional wavelet
Platform: | Size: 1852416 | Author: sansfroid | Hits:

[VHDL-FPGA-Verilog] DDR_FLASH_VHDL_Verilog

Description: FPGA DDR 外部RAM 读写的verilog代码，以及FLASH的vhdl代码-DDR SRAM READ AND WRITE VERILOG CODE ,FLASH VHDL CODE ,FPGA
Platform: | Size: 17408 | Author: rickdecent | Hits:

[Other] [EDACN-monthly]1

Description: Eda主要介绍的逻辑设计与集成电路：FPGA 设计的指导性原则（连载之二） 典型的FPGA 设计流程 大型复杂FPGA 设计推荐设计方式──Modular Design Coding Style 与综合前后仿真 数据接口设计 关于有限状态机编码的技巧和注意事项 做distributed ram 时遇到的几个不太明白的信号 Source Insight 兼容VHDL 与VERILOG 如何实现信号延时？ [转载]新手学习技巧-EDA introduces the logical design of integrated circuits: FPGA design of the guiding principles (Part II) Typical FPGA design flow Large, complex FPGA design recommended design approach ─ ─ Modular Design Coding Style and comprehensive before and after simulation Data interface design Finite state machine coding techniques and precautions Do the Distributed RAM encountered a few do not quite understand the signal Source Insight is compatible with VHDL and Verilog How to achieve signal delay? [Reserved] novice learning skills
Platform: | Size: 491520 | Author: 江风 | Hits:

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